View HYS64T6402_161714.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

D a t a S he et , Rev. 0.91, J u n e 2 00 4
HYS64T32000[G/H]DL-[3.7/5]-A HYS64T64020[G/H]DL-[3.7/5]-A HYS64T128021[G/H]DL-[3.7/5]-A
200-Pin Small Outline Dual-In-Line Memory Module SO-DIMM DDR2 SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2004-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S he et , Rev. 0.91, J u n e 2 00 4
HYS64T32000[G/H]DL-[3.7/5]-A HYS64T64020[G/H]DL-[3.7/5]-A HYS64T128021[G/H]DL-[3.7/5]-A
200-Pin Small Outline Dual-In-Line Memory Module SO-DIMM DDR2 SDRAM
Memor y Product s
Never
stop
thinking.
all
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A Revision History: Previous Revision: Page all all all Rev. 0.91 Rev. 0.83 2004-06 2003-09
Subjects (major changes since last revision) editorial changes removed HYS64T128022HDL products and all -3 products added HYS64T128021[G/]DL products
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.2_2003-10-07.fm
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Table of Contents 1 1.1 1.2 1.3 2 3 4 4.1 4.2 5 6 7 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 6 8
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IDD Specifications and Conditions
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 22 ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Electrical Characteristics & AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Data Sheet
5
Rev. 0.91, 2004-06 09122003-FTXN-KM26
200-Pin Small Outline Dual-In-Line Memory Module DDR2 SDRAM
HYS64T32000[G/H]DL-[3.7/5]-A HYS64T64020[G/H]DL-[3.7/5]-A HYS64T128021[G/H]DL-[3.7/5]-A
1
Overview
This chapter gives an overview of the 1.8 V 200-Pin Small Outline Dual-In-Line Memory Module, 256 MByte and 512 MByte and describes its main characteristics.
1.1
*
Features
* * * * * * * Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment(OCD) and On-Die Termination(ODT) Serial Presence Detect with E2PROM Low Profile Modules form factor: 67.60 mm x 30.00 mm (MO-224) Based on JEDEC standard reference layouts Raw Card "A", "C" and "D"
*
*
*
200-pin Non-ECC Unbuffered 8-Byte Dual-In-Line DDR2 SDRAM Module for Notebooks and other application where small form factors are required. One rank 32M x 64, two ranks 64M x 64 and 128M x 64 module organisation and 32M x 16 and 64M x 8 chip organisation JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply 256 ,512 MByte and 1GByte modules built with 512Mb DDR2 SDRAMs in 60-ball FBGA (P-TFBGA-60) and 84-ball FBGA (P-TFBGA-84) chipsize packages Performance -3.7
Table 1
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-5 PC2-3200 3-3-3 200 200 200 15 15 40 55
Units -- MHz MHz MHz ns ns ns ns
PC2-4200 4-4-4
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1.2
Description
The memory array is designed with 512Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The INFINEON HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A module family are low profile SO-DIMM modules with 30,0 mm height based on DDR2 technology. DIMMs are available as Non-ECC modules in 32M x 64 (256 MByte),64M x 64 (512 MByte) and 128M x 64 (1 GByte) organisation and density, intended for mounting into 200-pin connector sockets.
Data Sheet
6
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 2
Ordering Information Compliance Code PC2-4200S-444-10-C0 PC2-4200S-444-10-A0 PC2-4200S-444-10-D0 PC2-3200S-333-10-C0 PC2-3200S-333-10-A0 PC2-3200S-333-10-D0 Description one rank 256 MByte SO-DIMM two ranks 512 MByte SO-DIMM two ranks 1 GByte SO-DIMM one rank 256 MByte SO-DIMM two ranks 512 MByte SO-DIMM two ranks 1 GByte SO-DIMM SDRAM Technology 512 Mbit (x16) 512 Mbit (x16) 512 Mbit (x 8) 512 Mbit (x16) 512 Mbit (x16) 512 Mbit (x 8)
Product Type HYS64T32000GDL-3.7-A HYS64T64020GDL-3.7-A HYS64T128021GDL-3.7-A HYS64T32000GDL-5-A HYS64T64020GDL-5-A HYS64T128021GDL-5-A
HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A HYS64T128021HDL-3.7-A HYS64T32000HDL-5-A HYS64T64020HDL-5-A HYS64T128021HDL-5-A
PC2-4200S-444-10-C0 PC2-4200S-444-10-A0 PC2-4200S-444-10-D0 PC2-3200S-333-10-C0 PC2-3200S-333-10-A0 PC2-3200S-333-10-D0
one rank 256 MByte SO-DIMM two ranks 512 MByte SO-DIMM two ranks 1 GByte SO-DIMM one rank 256 MByte SO-DIMM two ranks 512 MByte SO-DIMM two ranks 1 GByte SO-DIMM
512 Mbit (x16) 512 Mbit (x16) 512 Mbit (x 8) 512 Mbit (x16) 512 Mbit (x16) 512 Mbit (x 8)
Note: The Compliance Code is printed on the module label and describes the speed grade,e.g. "512MB 2Rx16 PC2-3200S-33310-A" where "512MB" tells the density in megabytes, "2Rx16" means 2 ranks on module built of x16 components, "PC2-3200S" means DDR2 SO-DIMM with 4.26 GB/s module bandwidth and "44411" means CAS latency of 4, RCD1) latency of 4, and RP2) latency of 4 using Jedec SPD revision 1.0. All part numbers end with a place code, designating the silicon die revision. Example: HYS64T32000GDL-3.7- A, indicating Rev. A dice are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 8 of this datasheet. Table 3 DIMM Density 256 MB 512 MB 1 GB Address Format Module Organization 32M x64 64M x64 128M x64 Memory Ranks 1 2 2 # of SDRAMs 4 8 16 # of row/bank/column bits 13/2/10 13/2/10 14/2/10 Raw Card C A D
1) RCD: Row Column Delay 2) RP: Row Precharge
Data Sheet
7
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 4
Components on Modules1) DRAM Components HYB18T512160AC HYB18T512160AF2) HYB18T512800AC HYB18T512800AF
2)
Product Type HYS64T32000GDL HYS64T64020GDL HYS64T32000HDL2) HYS64T64020HDL
2)
DRAM Density 512 Mbit 512 Mbit 512 Mbit 512 Mbit
DRAM Organisation 32M x16 32M x16 64M x8 64M x8
HYS64T128021GDL HYS64T128021HDL
2) Green Product
2)
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
1.3
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 Table 5 Pin# Clock Signals 30 164 32 166 79 80 CK0 CK1 CK0 CK1 CKE0 CKE1 NC Control Signals 110 115 S0 S1 NC 108 113 109 Address Signals 107 106 102 101 100 99 98 Data Sheet BA0 BA1 A0 A1 A2 A3 A4 I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL 8 Rev. 0.91, 2004-06 09122003-FTXN-KM26 Address Bus 4:0 Bank Address Bus 1:0 RAS CAS WE I I NC I I I SSTL SSTL -- SSTL SSTL SSTL Chip Select Rank 0 Chip Select Rank 1 Note: 2-rank module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL -- Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Complement Clock Signals 2:0 Clock Signals 2:0 Pin Configuration of SO-DIMM Name Pin Type Buffer Type Function
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# 97 94 92 93 91 105 90 89 116 Pin Configuration of SO-DIMM (cont'd) Name A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC Data Signals 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 26:0 Pin Type I I I I I I I I I I NC Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- Address Signal 12 Address Signal 13 Note: 512M x4/x8 Note: Module based on 512 Mbit x16 Function Address Bus 11:5
Data Sheet
9
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 Data Strobe Signals Pin Configuration of SO-DIMM (cont'd) Name DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Bus 63:27
Data Sheet
10
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 Data Mask Signals 10 26 52 67 130 147 170 185 EEPROM 197 195 198 200 Power Supplies 1 199 81,82,87,88,95,96,103,104, 111,112,117,118 SCL SDA SA0 SA1 I I/O I I CMOS OD CMOS CMOS I/O Reference Voltage EEPROM Power Supply Power Supply Ground Plane Serial Bus Clock Serial Bus Data Slave Address Select Bus 2:0 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask Bus 7:0 Pin Configuration of SO-DIMM (cont'd) Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Complement Data Strobe Bus 7:0 Note: See block diagram for corresponding DQ signals Function Data Strobe Bus 7:0 Note: See block diagram for corresponding DQ signals
VREF AI -- VDDSPD PWR -- VDD PWR --
GND --
2,3,8,9,12,15,18,21,24,27,28, VSS 33,34,39,40,41,42,47,48,53, 54,59,60,65,66,71,72,77,78, 121,122,127,128,132,133,138, 139,144,145,149,150,155,156, 161,162,165,168,171,172,177, 178,183,184,187,190,193,196 Data Sheet
11
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview Table 5 Pin# Other Pins 114 119 50,69,83,84,85,120,163 ODT0 ODT1 NC NC NC -- On-Die Termination Control 0 On-Die Termination Control 1 Note: 1 Rank modules Not connected Note: Pins not connected on Infineon SO-DIMMs Table 6
Abbreviation I O I/O AI PWR GND NC
Pin Configuration of SO-DIMM (cont'd) Name Pin Type Buffer Type Function
Abbreviations for Pin Type
Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Table 7 Abbreviation SSTL LV-CMOS
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Data Sheet
12
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
V REF DQ0 V SS DQS0 DQ2 V SS DQ9 DQS1 V SS DQ11
-
Pin 001 Pin 005 Pin 009 Pin 013 Pin 017 Pin 021 Pin 025 Pin 029 Pin 033 Pin 037
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 DQ10 V SS
-
Pin 003 Pin 007 Pin 011 Pin 015 Pin 019 Pin 023 Pin 027 Pin 031 Pin 035 Pin 039
Pin 004 Pin 008 Pin 012 Pin 016 Pin 020 Pin 024 Pin 028 Pin 032 Pin 036 Pin 040
-
DQ4 V SS V SS DQ7 DQ12 V SS V SS CK0 DQ14 V SS
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038
-
V SS DQ5 DM0 DQ6 V SS DQ13 DM1 CK0 V SS DQ15
V SS DQ17 DQS2 V SS DQ19 DQ24 V SS NC DQ26 V SS V DD NC A12 A8 A5 A1 A10/AP WE CAS V DD V SS DQ33 DQS4 V SS DQ35 DQ40 V SS V SS DQ43 DQ48 V SS V SS DQS6 DQ50 V SS DQ57 DM7 DQ58 V SS SCL
-
Pin 041 Pin 045 Pin 049 Pin 053 Pin 057 Pin 061 Pin 065 Pin 069 Pin 073 Pin 077 Pin 081 Pin 085 Pin 089 Pin 093 Pin 097 Pin 101 Pin 105 Pin 109 Pin 113 Pin 117 Pin 121 Pin 125 Pin 129 Pin 133 Pin 137 Pin 141 Pin 145 Pin 149 Pin 153 Pin 157 Pin 161 Pin 165 Pin 169 Pin 173 Pin 177 Pin 181 Pin 185 Pin 189 Pin 193 Pin 197
DQ16 V SS DQS2 DQ18 V SS DQ25 DM3 V SS DQ27 CKE0 NC V DD A9 V DD A3 V DD BA0 V DD NC/CS1 ODT1 DQ32 V SS DQS4 DQ34 V SS DQ41 DM5 DQ42 V SS DQ49 NC DQS6 V SS DQ51 DQ56 V SS V SS DQ59 SDA V DD SPD
-
Pin 043 Pin 047 Pin 051 Pin 055 Pin 059 Pin 063 Pin 067 Pin 071 Pin 075 Pin 079 Pin 083 Pin 087 Pin 091 Pin 095 Pin 099 Pin 103 Pin 107 Pin 111 Pin 115 Pin 119 Pin 123 Pin 127 Pin 131 Pin 135 Pin 139 Pin 143 Pin 147 Pin 151 Pin 155 Pin 159 Pin 163 Pin 167 Pin 171 Pin 175 Pin 179 Pin 183 Pin 187 Pin 191 Pin 195 Pin 199
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 Pin 188 Pin 192 Pin 196 Pin 200
-
DQ20 V SS DM2 DQ22 V SS DQ29 DQS3 V SS DQ31 NC/CKE1 NC V DD A7 V DD A2 V DD RAS V DD A13 NC DQ36 V SS V SS DQ39 DQ44 V SS DQS5 DQ46 V SS DQ53 CK1 V SS V SS DQ55 DQ60 V SS DQS7 DQ62 V SS SA1
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 Pin 186 Pin 190 Pin 194 Pin 198
-
V SS DQ21 NC V SS DQ23 DQ28 V SS DQS3 DQ30 V SS V DD A14 A11 A6 A4 A0 BA1 CS0 ODT0 V DD V SS DQ37 DM4 DQ38 V SS DQ45 DQS5 V SS DQ47 DQ52 V SS CK1 DM6 DQ54 V SS DQ61 DQS7 V SS DQ63 SA0 MPPT0140
FRONTSIDE
Figure 1
Pin Configuration SO-DIMM (200 Pin)
Data Sheet
13
BACKSIDE
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Overview
Table 8 Symbol CK[1:0], CK[1:0]
Input/Output Functional Description Type I Polarity Function Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down Mode or the Self Refresh Mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. Selects internal SDRAM memory bank Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0] inputs. If AP is low, then BA[1:0] are used to define which bank to precharge. Data Input/Output pins The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm resistor and DDR2 SDRAM mode registers programmed appropriately. Power supplies for core, I/O, Serial Presence Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to VDDSPD on the motherboard to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. Address pins used to select the Serial Presence Detect base address.
CKE[1:0]
I
Active High Active Low
S[1:0]
I
RAS, CAS, I WE BA[1:0] ODT[1:0] A[9:0], A10/AP, A[13:11] I I I
Active Low -- Active High --
DQ[63:0] DM[7:0]
I/O I
-- Active High Cross point
DQS[7:0], DQS[7:0]
I/O
VDD, Supply -- VDDSPD, VSS
SDA I/O --
SCL SA[1:0]
I I
-- --
Data Sheet
14
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
2
Block Diagrams
CS0 3.0+/- 5% CS CS
DQS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
DQS4 DQS4 DM4
D0
DQS5 DQS5 DM5
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
D2
DQS2 DQS2 DM2
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
DQS6 DQS6 DM6
D1
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D3
VDDSPD
EEPROM D0 - D3 (VDD&VDDQ) D0 - D3 D0 - D3
Serial PD SDA SCL WP A0 A1 A2
Clock Wiring Clock Input CK0, CK0 CK1, CK1 SDRAMs 2 SDRAMs 2 SDRAMs
VDD VREF V SS
SA0 SA1
3.0+/- 5% BA0, BA1 BA0, BA1 : SDRAMs D0 - D3 A0 - A12 A0 - A12 : SDRAMs D0 - D3 RAS RAS : SDRAMs D0 - D3 CAS CAS : SDRAMs D0 - D3 WE WE : SDRAMs D0 - D3 CKE0 ODT0 CKE ODT : SDRAMs D0 - D3 : SDRAMs D0 - D3
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown DQ/DQS/DQS/DM resistors are 22 +/- 5% Address and control resistors are 3.0 +/- 5%
Figure 2 Note
Block Diagram Raw Card C (32M x 64, 1 rank, x16)
1. DQ, DQS, DQS, DM resistors are 22 5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1, CKEO, CKE1 resistors are 3 5 %
Data Sheet
15
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
CS1 CS0 DQS0 DQS0 DM0
3.0+/- 5%
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D0
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
DQS4 DQS4 DM4
D4
DQS5 DQS5 DM5
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D2
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D6
DQS2 DQS2 DM2
DQS3 DQS3 DM3
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
D1
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
DQS6 DQS6 DM6
D5
DQS7 DQS7 DM7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/ O 12 I/O 13 I/0 14 I/O 15
CS
D3
LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/0 14 I/O 15
CS
D7
VDDSPD
EEPROM D0 - D7 (VDD & VDDQ) D0 - D7 D0 - D7
Serial PD SDA SCL WP A0 A1 A2
Clock Wiring Clock Input CK0, CK0 CK1, CK1 SDRAMs 4 SDRAMs 4 SDRAMs
VDD VREF V SS
SA0 SA1
BA0, BA1 A0 - A12 RAS CAS WE CKE0 CKE1 ODT0 ODT1
BA0, BA1 : SDRAMs D0 - D3 A0 - A12 : SDRAMs D0 - D3 RAS : SDRAMs D0 - D3 CAS : SDRAMs D0 - D3 WE CKE CKE ODT ODT : SDRAMs D0 - D3 : SDRAMs D0 - D3 : SDRAMs D4 - D7 : SDRAMs D0 - D3 : SDRAMs D4 - D7
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS/DM/CKE/CS relationships must be maintained as shown DQ/DQS/DQS/DM resistors are 22 +/- 5% Address and control resistors are 3.0 +/- 5%
Figure 3 Note
Block Diagram Raw Card A (64M x 64, 2 ranks, x16)
1. DQ, DQS, DQS, DM resistors are 22 5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1, CKEO, CKE1 resistors are 3 5 %
Data Sheet
16
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Block Diagrams
10 +/- 5% CKE1 ODT1 CS1 CKE0 ODT0 CS0 DQS0 DQS0 DM0 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS0 ODT0 CKE0 CS1 ODT1 CKE1 DQS4 DQS4 DM4 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VDDSPD SDA SCL WP A0 A1 A2 CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
D0, D8 (dual die)
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
D4, D12 (dual die)
DQS1 DQS1 DM1
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS5 DQS5 DM5
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D1, D0 (dual die) D1, D9 (dual die)
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
D5, D13 (dual die)
DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQS6 DQS6 DM6
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D2, D10 (dual die) D2, D10 (dual die)
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
D6, D14 (dual die)
CS0 ODT0 CKE0 CS1 ODT1 CKE1
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DQS7 DM7
CS0 ODT0 CKE0 CS1 ODT1 CKE1
D3, D11 (dual die)
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
D7, D15 (dual die)
Serial PD
EEPROM
VDD VREF V SS Clock Wiring Clock Input CK0, CK0 CK1, CK1 SDRAMs 8 loads 8 loads
D0 - D15, VDD, VDDQ D0 - D15 D0 - D15
SA0 SA1 10 +/- 5% BA0, BA1 A0 - A13 RAS CAS WE BA0, BA1 : SDRAMs D0 - D15 A0 - A13 : SDRAMs D0 - D15 RAS : SDRAMs D0 - D15 CAS : SDRAMs D0 - D15 WE : SDRAMs D0 - D15
Unless otherwise noted, resistor values are 22 +/- 5%. DQ wiring may differ from that described in this drawing, however DQ, DM, DQS, DQS relationship are maintained as shown
Figure 4 Note
Block Diagram Raw Card D (128M x 64, 2 ranks, x8)
1. DQ, DQS, DQS, DM resistors are 22 5 %
2. S0, S1, BAn, An, RAS, CAS, WE, ODT0, ODT1, CKEO, CKE1 resistors are 3 5 %
Data Sheet
17
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics
3
Table 9 Parameter
Electrical Characteristics
Absolute Maximum Ratings Symbol Limit Values Min. Max. 2.3 2.3 2.3 +105 95 kPa % V V - 0.5 - 1.0 - 0.5 +69 5 Unit Note/Test Condition
1) 1) 1) 1) 1)
Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Barometric Pressure (operating & storage) Storage Humidity (without condensation)
VIN, VOUT VDD VDDQ HSTG
1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 10 Parameter DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Storage temperature Barometric Pressure (operating & storage) Operating Humidity (relative) Operating Temperature Range Symbol Limit Values min. max. +65 +95 +100 +105 90 C C C kPa %
5) 1)2)3)4)
Unit
Notes
TOPR TCASE TSTG HOPR
0 0 - 55 +69 10
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2 2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported 3) Above 85 C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation. 5) Up to 3000 m.
Table 11 Parameter
Supply Voltage Levels and DC Operating Conditions Symbol Limit Values Min. Nom. 1.8 1.8 0.5 x VDDQ -- -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V A
3) 1) 2)
Unit
Notes
Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30 -5
VDDQ +0.3 VREF -0.125
5
1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 3) For any pin on the DIMM connector under test input of 0 V VIN VDDQ + 0.3 V.
Data Sheet
18
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4
Table 12 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions1)2)
Symbol
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD1
IDD2P IDD2N
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
Distributed Refresh Current IDD5D tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
19
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions Table 12 Parameter
IDD Measurement Conditions1)2) (cont'd)
Symbol
IDD6 Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85 C max.
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
2) For details and notes see the relevant INFINEON component data sheet
Table 13
IDD Specification HYS64T[32000/64020][G/H]DL
HYS64T32000GDL-3.7-A HYS64T64020GDL-3.7-A HYS64T32000HDL-3.7-A HYS64T64020HDL-3.7-A Unit Notes HYS64T32000GDL-5-A HYS64T64020GDL-5-A HYS64T32000HDL-5-A HYS64T64020HDL-5-A 512 MB x64 Max. 300 320 30 260 200 100 40 280 360 380 500 50 30 860
Product Type
Organization
256 MB 256 MB 512 MB x64 1 Rank x64 1 Rank Max. 280 300 20 130 100 50 20 140 340 360 480 20 20 840 x64 Max. 300 320 30 260 200 100 40 280 360 380 500 50 30 860
256 MB 256 MB 512 MB x64 Max. 320 360 20 160 120 60 20 160 400 440 520 20 20 880 x64 1 Rank Max. 320 360 20 160 120 60 20 160 400 440 520 20 20 880 x64 Max. 340 380 30 320 240 130 40 320 420 460 540 50 30 900
512 MB x64 Max. 340 380 30 320 240 130 40 320 420 460 540 50 30 900 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1)2) 1)2) 1)3) 1)3) 1)3) 1)3) 1)3) 1)3) 1)2) 1)2) 1)2) 1)3) 1)4) 1)2)
2 Ranks 2 Ranks 1 Rank
2 Ranks 2 Ranks
Symbol
Max. 280 300 20 130 100 50 20 140 340 360 480 20 20 840
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode 4) standard
Data Sheet
20
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
Table 14
IDD Specification HYS64T128021[G/H]DL
HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A HYS64T128021HDL-5-A Unit Notes
Product Type
Organization
1 GB x64 2 Ranks
1 GB x64 2 Ranks Max. 472 512 64 512 400 208 80 560 592 632 976 96 64 1072
1 GB x64 2 Ranks Max. 552 632 64 640 480 256 80 640 752 792 1060 96 64 1312
1 GB x64 2 Ranks Max. 552 632 64 640 480 256 80 640 752 792 1060 96 64 1312 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1)2) 1)2) 1)3) 1)3) 1)3) 1)3) 1)3) 1)3) 1)2) 1)2) 1)2) 1)3) 1)4) 1)2)
Symbol
Max. 472 512 64 512 400 208 80 560 592 632 976 96 64 1072
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode 4) standard
Data Sheet
21
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
IDD Specifications and Conditions
4.1
IDD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 15 are used. Table 15 Parameter CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval
IDD Measurement Test Condition
Symbol CLmin -3.7 4 3.75 15 60 10 45 70000 15 105 7.8 -5 3 5 15 55 10 40 70000 15 105 7.8 Unit PC2-4200-4-4-4 PC2-3200-3-3-3
tCK
ns ns ns ns ns ns ns ns s
tCKmin tRCDmin tRCmin tRRDmin tRASmin tRASmax tRPmin tRFCmin tREFI
4.2
ODT (On Die Termination) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 16 Parameter Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. ODT current per terminated pin
Symbol
Min. Typ. Max. 5 2.5 10 5 6 3 12 6 7.5 3.75 15 7.5
Unit mA/DQ mA/DQ mA/DQ mA/DQ
EMRS(1) State A6 = 0, A2 = 1 A6 = 1, A2 = 0 A6 = 0, A2 = 1 A6 = 1, A2 = 0
IODTO IODTT
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
22
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
5
Table 17 Parameter
Electrical Characteristics & AC Timings
AC Timing - Absolute Specificatioins -5/-3.7 Symbol -3.7 PC2-4200S Min. Max. +500 +450 0.55 0.55 8000 8000 -- -- -- -- -- -- -5 PC2-3200S Min. -600 -500 0.45 0.45 min. (tCL, tCH) 5000 5000 600 600 400 400 0.6 0.35 -- 2xtACmin 8000 8000 -- -- -- -- -- -- Max. +600 +500 0.55 0.55 ps ps
1) 1) 1) 1) 1) 1)2) 1)3) 1) 1) 1) 1) 1)
Unit Notes
tAC DQS output access time from CK/CK tDQSCK CK, CK high-level width tCH CK, CK low-level width tCL Clock Half Period tHP Clock cycle time tCK
DQ output access time from CK/CK Address and control input setup time tIS Address and control input hold time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK DQ low-impedance from CK / CK DQS low-impedance from CK / CK DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor
-500 -450 0.45 0.45 min. (tCL, tCH) 5000 3750 600 600 350 350 0.6 0.35 -- 2xtACmin
tCK tCK tCK
ps ps ps ps ps ps
tIH tDH tDS tIPW tDIPW tHZ tLZ(DQ) tLZ(DQS) tDQSQ
tCK tCK
ps ps ps ps ps
1)
tACmax tACmax tACmax
300 400 --
tACmax tACmax tACmax
350 450 --
1)
1) 1) 1)
tACmin
-- --
tACmin
-- --
tQHS Data Output hold time from DQS tQH Write command to 1st DQS latching tDQSS
transition DQS input low (high) pulse width (write cycle) DQS falling edge to CLK setup time (write cycle)
1) 1) 1)
tHP-tQHS
WL - 0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45
tHP-tQHS
WL + 0.25 WL - 0.25 -- -- -- -- -- 0.60 1.1 0.60 70000 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 40
tCK WL + 0.25 tCK
-- -- -- -- -- 0.60 1.1 0.60 70000
tDQSL,H tDSS
tCK tCK tCK tCK tCK tCK tCK tCK
ns
1)
1)
DQS falling edge hold time from CLK tDSH (write cycle) Mode register set command cycle time Write preamble Write postamble Read preamble Read postamble Active to Precharge command
1)
tMRD tWPRE tWPST tRPRE tRPST tRAS
1)
1) 1) 1) 1) 1)
Data Sheet
23
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings Table 17 Parameter AC Timing - Absolute Specificatioins -5/-3.7 Symbol -3.7 PC2-4200S Min. Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay (with and without Auto-Precharge) delay Precharge command period Active bank A to Active bank B command CAS A to CAS B Command Period Write recovery time Auto precharge write recovery + precharge time Max. -- -- -- -- -- -- -- -- -- -- -- -5 PC2-3200S Min. 55 105 15 15 10 2 15 WR + tRP 10 7.5 2 Max. -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns
1)
Unit Notes
tRC tRFC tRCD tRP tRRD tCCD tWR tDAL
60 105 15 15 10 2 15 WR + tRP 7.5 7.5 2
1)
1)
1) 1)
tCK
ns
1) 1) 1)
tCK
ns ns
Internal write to read command delay tWTR Internal read to precharge command tRTP delay Exit power down to any valid command (other than NOP or Deselect)
1) 1)
tXARD
tCK
1)
Exit active power-down mode to read tXARDS command (slew exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to read command Exit Self-Refresh to non-read command CKE minimum high and low pulse width OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops low Average Periodic Refresh Interval
6 - AL 2
-- --
6 - AL 2
-- --
tCK tCK
1)
tXP
1)
tXSRD tXSNR tCKE tOIT tDELAY tREFI
200
-- -- -- 12
200
-- -- -- 12
tCK
ns
1) 1)
tRFC + 10
3 0
tRFC + 10
3 0
tCK
ns ns s
1)
1) 1)
tIS + tCK + tIH --
-- -- 7.8 3.9
tIS + tCK+ tIH --
-- -- 7.8 3.9
1)4) 1)5)
1) For details and notes see the relevant INFINEON component datasheet 2) CL = 3 3) CL = 4 & 5 4) 0 C
TCASE 85 C
5) 85 C < TCASE 95 C
Data Sheet
24
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Electrical Characteristics & AC Timings
Table 18 Symbol
ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off delay (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency Min. 2 Max. 2 Unit
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
tAC(min) tAC(min) + 2 ns
2.5
tAC(max) + 1 ns 2 tCK + tAC(max) + 1 ns
2.5
tCK
ns ns
tAC(min) tAC(min) + 2 ns
3 8
tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns
-- --
tCK tCK
Data Sheet
25
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
6
Table 19
SPD Codes
SPD Codes for HYS 64T[32000/64020] PC2-4200S HYS64T64020GDL-3.7-A HYS64T32000GDL-3.7-A HYS64T64020HDL-3.7-A HYS64T32000HDL-3.7-A 256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 10 00 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-4200S-444 Rev. 1.1 HEX 80 08 08 0D 0A 61 40 00 05 3D 50 00
256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 3D 50 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 Description Programmed SPD Bytes in EEPROM
PC2-4200S-444 Rev. 1.1 HEX 80
Total number of Bytes 08 in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level [ns] 08 0D 0A 61 40 00 05
tCK @ CLmax (Byte 18) 3D tAC SDRAM @ CLmax
(Byte 18) [ns] Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width 00 50
12 13 14
82 10 00
82 10 00
82 10 00
Data Sheet
26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 19 SPD Codes for HYS 64T[32000/64020] PC2-4200S HYS64T64020GDL-3.7-A HYS64T32000GDL-3.7-A HYS64T64020HDL-3.7-A HYS64T32000HDL-3.7-A 256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 00 0C 04 38 00 04 00 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-4200S-444 Rev. 1.1 HEX 00 0C 04 38 00 04 00 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22 27
256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 00 0C 04 38 00 04 00 01 3D 50 50 60 3C 28 3C 2D 40 25 37 10 22
Label Code JEDEC SPD Revision Byte# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Description Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes
PC2-4200S-444 Rev. 1.1 HEX 00 0C 04 38 00 04 00 3D
Component Attributes 01
tCK @ CLmax -1 (Byte 18) [ns]
1 [ns]
tAC SDRAM @ CLmax - 50 tCK @ CLmax -2 (Byte 18) [ns]
2 [ns] 50
tAC SDRAM @ CLmax - 60 tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank 3C 28 3C 2D 40 25 37 10 22
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns]
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 19 SPD Codes for HYS 64T[32000/64020] PC2-4200S HYS64T64020GDL-3.7-A HYS64T32000GDL-3.7-A HYS64T64020HDL-3.7-A HYS64T32000HDL-3.7-A 256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 2B 1D 1D 23 16 36 1C 30 00 00 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-4200S-444 Rev. 1.1 HEX 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 2B
256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52 2B
Label Code JEDEC SPD Revision Byte# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description
PC2-4200S-444 Rev. 1.1 HEX 3C 1E 1E 00 00 3C 69 80 1E 28 00 53 72 52
tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta /
T4R4W Delta T0 (DT0) Psi(T-A) DRAM
T2N (DT2N, UDIMM) 2B or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) 1D 1D 23
51 52 53 54 55 56 57 58 59
1D 1D 23 16 36 1C 30 00 00 28
1D 1D 23 16 36 1C 30 00 00
T3P.slow (DT3P slow) 16 T4R (DT4R) / T4R4W 36 S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG 1C 30 00 00
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 19 SPD Codes for HYS 64T[32000/64020] PC2-4200S HYS64T64020GDL-3.7-A HYS64T32000GDL-3.7-A HYS64T64020HDL-3.7-A HYS64T32000HDL-3.7-A 256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 00 00 11 BB C1 00 00 00 00 00 00 00 xx 36 34 54 33 32 30 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-4200S-444 Rev. 1.1 HEX 00 00 11 BC C1 00 00 00 00 00 00 00 xx 36 34 54 36 34 30
256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 00 00 11 BB C1 00 00 00 00 00 00 00 xx 36 34 54 33 32 30
Label Code JEDEC SPD Revision Byte# 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Description TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
PC2-4200S-444 Rev. 1.1 HEX 00 00 11
Checksum of Bytes 0- BC 62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location C1 00 00 00 00 00 00 00 xx
Product Type, Char 1 36 Product Type, Char 2 34 Product Type, Char 3 54 Product Type, Char 4 36 Product Type, Char 5 34 Product Type, Char 6 30
Data Sheet
29
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 19 SPD Codes for HYS 64T[32000/64020] PC2-4200S HYS64T64020GDL-3.7-A HYS64T32000GDL-3.7-A HYS64T64020HDL-3.7-A HYS64T32000HDL-3.7-A 256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 30 30 48 44 4C 33 2E 37 41 20 20 20 1x xx xx xx xx Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-4200S-444 Rev. 1.1 HEX 32 30 48 44 4C 33 2E 37 41 20 20 20 1x xx xx xx xx
256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX 30 30 47 44 4C 33 2E 37 41 20 20 20 1x xx xx xx xx
Label Code JEDEC SPD Revision Byte# 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Description
PC2-4200S-444 Rev. 1.1 HEX
Product Type, Char 7 32 Product Type, Char 8 30 Product Type, Char 9 47 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code 44 4C 33 2E 37 41 20 20 20 1x xx
Module Manufacturing xx Date Year Module Manufacturing xx Date Week Module Manufacturing xx Date Week
Data Sheet
30
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 19 SPD Codes for HYS 64T[32000/64020] PC2-4200S HYS64T64020GDL-3.7-A HYS64T32000GDL-3.7-A HYS64T64020HDL-3.7-A HYS64T32000HDL-3.7-A 256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX xx xx xx xx 00 FF Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-4200S-444 Rev. 1.1 HEX xx xx xx xx 00 FF
256 MB x64 1 Rank (x16) PC2-4200S-444 Rev. 1.1 HEX xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 96 97 98 99 100 127 128255 Description
PC2-4200S-444 Rev. 1.1 HEX
Module Serial Number xx (1) Module Serial Number xx (2) Module Serial Number xx (3) Module Serial Number xx (4) Not used BLANK 00 FF
Data Sheet
31
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
Table 20
SPD Codes for HYS 64T[32000/64020] PC2-3200S HYS64T64020GDL-5-A HYS64T32000GDL-5-A HYS64T64020HDL-5-A HYS64T32000HDL-5-A 256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 50 60 00 82 10 00 00 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-3200S-333 Rev. 1.1 HEX 80 08 08 0D 0A 61 40 00 05 50 60 00
256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 50 60 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 Description Programmed SPD Bytes in EEPROM
PC2-3200S-333 Rev. 1.1 HEX 80
Total number of Bytes 08 in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level [ns] 08 0D 0A 61 40 00 05
tCK @ CLmax (Byte 18) 50 tAC SDRAM @ CLmax
(Byte 18) [ns] Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used 00 60
12 13 14 15
82 10 00 00
82 10 00 00
82 10 00 00
Data Sheet
32
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 20 SPD Codes for HYS 64T[32000/64020] PC2-3200S HYS64T64020GDL-5-A HYS64T32000GDL-5-A HYS64T64020HDL-5-A HYS64T32000HDL-5-A 256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 0C 04 38 00 04 00 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-3200S-333 Rev. 1.1 HEX 0C 04 38 00 04 00 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C
256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 0C 04 38 00 04 00 01 50 60 50 60 3C 28 3C 2D 40 35 47 15 27 3C
Label Code JEDEC SPD Revision Byte# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Description Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes
PC2-3200S-333 Rev. 1.1 HEX 0C 04 38 00 04 00 50
Component Attributes 01
tCK @ CLmax -1 (Byte 18) [ns]
1 [ns]
tAC SDRAM @ CLmax - 60 tCK @ CLmax -2 (Byte 18) [ns]
2 [ns] 50
tAC SDRAM @ CLmax - 60 tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank 3C 28 3C 2D 40 35 47 15 27 3C
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns] tWR.min [ns]
Data Sheet
33
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 20 SPD Codes for HYS 64T[32000/64020] PC2-3200S HYS64T64020GDL-5-A HYS64T32000GDL-5-A HYS64T64020HDL-5-A HYS64T32000HDL-5-A 256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 23 1D 19 1C 16 2E 1A 2D 00 00 00 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-3200S-333 Rev. 1.1 HEX 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 23
256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 28 1E 00 00 3C 69 80 23 2D 00 51 72 42 23
Label Code JEDEC SPD Revision Byte# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description
PC2-3200S-333 Rev. 1.1 HEX 28 1E 00 00 3C 69 80 23 2D 00 51 72 42
tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta /
T4R4W Delta T0 (DT0) Psi(T-A) DRAM
T2N (DT2N, UDIMM) 23 or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) 1D 19 1C
51 52 53 54 55 56 57 58 59 60
1D 19 1C 16 2E 1A 2D 00 00 00
1D 19 1C 16 2E 1A 2D 00 00 00
T3P.slow (DT3P slow) 16 T4R (DT4R) / T4R4W 2E S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) 1A 2D 00 00 00
Data Sheet
34
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 20 SPD Codes for HYS 64T[32000/64020] PC2-3200S HYS64T64020GDL-5-A HYS64T32000GDL-5-A HYS64T64020HDL-5-A HYS64T32000HDL-5-A 256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 00 11 0D C1 00 00 00 00 00 00 00 xx 36 34 54 33 32 30 30 30 Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-3200S-333 Rev. 1.1 HEX 00 11 0E C1 00 00 00 00 00 00 00 xx 36 34 54 36 34 30 32 30 35
256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 00 11 0D C1 00 00 00 00 00 00 00 xx 36 34 54 33 32 30 30 30
Label Code JEDEC SPD Revision Byte# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Description TREG (DTREG) / Toggle Rate SPD Revision
PC2-3200S-333 Rev. 1.1 HEX 00 11
Checksum of Bytes 0- 0E 62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location C1 00 00 00 00 00 00 00 xx
Product Type, Char 1 36 Product Type, Char 2 34 Product Type, Char 3 54 Product Type, Char 4 36 Product Type, Char 5 34 Product Type, Char 6 30 Product Type, Char 7 32 Product Type, Char 8 30
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 20 SPD Codes for HYS 64T[32000/64020] PC2-3200S HYS64T64020GDL-5-A HYS64T32000GDL-5-A HYS64T64020HDL-5-A HYS64T32000HDL-5-A 256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 48 44 4C 35 41 20 20 20 20 20 1x xx xx xx xx xx Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-3200S-333 Rev. 1.1 HEX 48 44 4C 35 41 20 20 20 20 20 1x xx xx xx xx xx
256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX 47 44 4C 35 41 20 20 20 20 20 1x xx xx xx xx xx
Label Code JEDEC SPD Revision Byte# 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Description Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code
PC2-3200S-333 Rev. 1.1 HEX 44 4C 35 41 20 20 20 20 20 1x xx
Product Type, Char 9 47
Module Manufacturing xx Date Year Module Manufacturing xx Date Week Module Manufacturing xx Date Week Module Serial Number xx (1)
Data Sheet
36
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 20 SPD Codes for HYS 64T[32000/64020] PC2-3200S HYS64T64020GDL-5-A HYS64T32000GDL-5-A HYS64T64020HDL-5-A HYS64T32000HDL-5-A 256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX xx xx xx 00 FF Rev. 0.91, 2004-06 09122003-FTXN-KM26
Product Type
Organization
512 MB x64 2 Ranks (x16)
512 MB x64 2 Ranks (x16) PC2-3200S-333 Rev. 1.1 HEX xx xx xx 00 FF
256 MB x64 1 Rank (x16) PC2-3200S-333 Rev. 1.1 HEX xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 97 98 99 100 127 128255 Description
PC2-3200S-333 Rev. 1.1 HEX
Module Serial Number xx (2) Module Serial Number xx (3) Module Serial Number xx (4) Not used BLANK 00 FF
Data Sheet
37
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes
Table 21
SPD Codes for HYS64T128021[G/H]DL HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 50 60 00 82 08 00 00 Rev. 0.91, 2004-06 09122003-FTXN-KM26 HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 50 60 00 82 08 00 00 38
Product Type
Organization
1 GByte x64 2 Ranks (x8)
1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 40 00 05 3D 50 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 Description Programmed SPD Bytes in EEPROM
PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 80
PC2-3200S-444 PC2-3200S-444
Total number of Bytes 08 in EEPROM Memory Type (DDR2) 08 Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level 0E 0A 61 40 00 05
tCK @ CLmax (Byte 18) 3D [ns] tAC SDRAM @ CLmax
(Byte 18) [ns] Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used 00 50
12 13 14 15
82 08 00 00
82 08 00 00
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 21 SPD Codes for HYS64T128021[G/H]DL HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 0C 04 38 00 04 00 01 50 60 50 60 3C 1E 3C 2D 80 35 47 15 27 Rev. 0.91, 2004-06 09122003-FTXN-KM26 HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 0C 04 38 00 04 00 01 50 60 50 60 3C 1E 3C 2D 80 35 47 15 27 39
Product Type
Organization
1 GByte x64 2 Ranks (x8)
1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 0C 04 38 00 04 00 01 3D 50 50 60 3C 1E 3C 2D 80 25 37 10 22
Label Code JEDEC SPD Revision Byte# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Description Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies Not used DIMM Type Information DIMM Attributes
PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 0C 04 38 00 04 00 3D
PC2-3200S-444 PC2-3200S-444
Component Attributes 01
tCK @ CLmax -1 (Byte 18) [ns]
1 [ns]
tAC SDRAM @ CLmax - 50 tCK @ CLmax -2 (Byte 18) [ns]
2 [ns] 50
tAC SDRAM @ CLmax - 60 tRP.min [ns] tRRD.min [ns] tRCD.min [ns] tRAS.min [ns]
Module Density per Rank 3C 1E 3C 2D 80 25 37 10 22
tAS.min and tCS.min [ns] tAH.min and tCH.min [ns] tDS.min [ns] tDH.min [ns]
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 21 SPD Codes for HYS64T128021[G/H]DL HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 Rev. 0.91, 2004-06 09122003-FTXN-KM26 HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 3C 28 1E 00 00 3C 69 80 23 2D 00 51 78 32 24 1E 1B 1E 17 28 1B 1E 00 00 40
Product Type
Organization
1 GByte x64 2 Ranks (x8)
1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E 2E
Label Code JEDEC SPD Revision Byte# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Description
PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 3C 1E 1E 00 00 3C 69 80 1E 28 00 51 78 3E
PC2-3200S-444 PC2-3200S-444
tWR.min [ns] tWTR.min [ns] tRTP.min [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.min [ns] tRFC.min [ns] tCK.max [ns] tDQSQ.max [ns] tQHS.max [ns]
PLL Relock Time
TCASE.max Delta /
T4R4W Delta T0 (DT0) Psi(T-A) DRAM
T2N (DT2N, UDIMM) 2E or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow)
S
51 52 53 54 55 56 57 58 59
1E 1E 24 17
1E 1E 24 17 34 1E 20 00 00
T4R (DT4R) / T4R4W 34 Sign (DT4R4W) T5B (DT5B) 1E 20 00 00
T7 (DT7) Psi(ca) PLL Psi(ca) REG
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 21 SPD Codes for HYS64T128021[G/H]DL HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 00 00 11 26 C1 00 00 00 00 00 00 00 xx 36 34 54 31 32 38 Rev. 0.91, 2004-06 09122003-FTXN-KM26 HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 00 00 11 26 C1 00 00 00 00 00 00 00 xx 36 34 54 31 32 38 41
Product Type
Organization
1 GByte x64 2 Ranks (x8)
1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 00 00 11 D2 C1 00 00 00 00 00 00 00 xx 36 34 54 31 32 38
Label Code JEDEC SPD Revision Byte# 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Description TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 00 00 11
PC2-3200S-444 PC2-3200S-444
Checksum of Bytes 0- D2 62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 C1 00 00 00 00 00 00 00 xx 36 34 54 31 32 38
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 21 SPD Codes for HYS64T128021[G/H]DL HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 30 32 31 47 44 4C 35 41 20 20 20 20 0x xx xx xx xx xx xx xx Rev. 0.91, 2004-06 09122003-FTXN-KM26 HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 30 32 31 48 44 4C 35 41 20 20 20 20 0x xx xx xx xx xx xx xx 42
Product Type
Organization
1 GByte x64 2 Ranks (x8)
1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX 30 32 31 47 44 4C 33 2E 37 41 20 20 0x xx xx xx xx xx xx xx
Label Code JEDEC SPD Revision Byte# 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Description Product Type, Char 7 Product Type, Char 8 Product Type, Char 9
PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX 30 32 31
PC2-3200S-444 PC2-3200S-444
Product Type, Char 10 48 Product Type, Char 11 44 Product Type, Char 12 4C Product Type, Char 13 33 Product Type, Char 14 2E Product Type, Char 15 37 Product Type, Char 16 41 Product Type, Char 17 20 Product Type, Char 18 20 Module Revision Code Test Program Revision Code 0x xx
Module Manufacturing xx Date Year Module Manufacturing xx Date Week Module Manufacturing xx Date Week Module Serial Number xx (1) Module Serial Number xx (2) Module Serial Number xx (3)
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
SPD Codes Table 21 SPD Codes for HYS64T128021[G/H]DL HYS64T128021GDL-3.7-A HYS64T128021HDL-3.7-A HYS64T128021GDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX xx 00 FF Rev. 0.91, 2004-06 09122003-FTXN-KM26 HYS64T128021HDL-5-A 1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX xx 00 FF 43
Product Type
Organization
1 GByte x64 2 Ranks (x8)
1 GByte x64 2 Ranks (x8) Rev. 1.1 HEX xx 00 FF
Label Code JEDEC SPD Revision Byte# 99 100 127 128255 Description
PC2-4200S-444 PC2-4200S-444 Rev. 1.1 HEX
PC2-3200S-444 PC2-3200S-444
Module Serial Number xx (4) Not used BLANK 00 FF
Data Sheet
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Package Outlines
7
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
4 0.1
(2.15)
1
17.55 0.1 2.7 0.1 (1.5)
(2.45)
100
30
10.1
0.15
11.4 0.1
47.4 0.1 (1.8)
(2.45)
2.4 0.1 10.1 101
(2.15)
4 0.1
200
6 0.1 20 0.1
2 MIN.
Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1 Burnished, no burr allowed
GLD09648
Figure 5
Package Outline L-DIM-200-30
Data Sheet
2.55
44
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Package Outlines
67.6 63.6 0.1 3.8 MAX.
1.8 0.05
4 0.1
(2.15)
1
17.55 0.1 2.7 0.1 (1.5)
(2.45)
100
30
10.1
0.15
11.4 0.1
47.4 0.1 (1.8)
(2.45)
4 0.1
2.4 0.1 10.1 101
(2.15)
6 0.1 20 0.1
200
2 MIN.
Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1 Burnished, no burr allowed
GLD09649
Figure 6
Package Outline L-DIM-200-31
Data Sheet
2.55
45
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Package Outlines
67.6 63.6
0.13
0.15
3.8 max.
30.00
1 2.15
39 11.4
41 47.4 4.2 2.7
199 2.45
0.
1 1
2.45 2 4
1.0 40 42 200
2.15
6
20
1.8 4
Detail of Contacts
Detail of Chamfer
2.55
0.25
0.2 -
0.15
0.45 0.6
0.2 0.15
Figure 7
Package Outline L-DIM-200-33
Data Sheet
46
Rev. 0.91, 2004-06 09122003-FTXN-KM26
HYS64T[32000/64020/128021][G/H]DL-[3.7/5]-A 512 Mbit DDR2 SDRAM
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
8
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 22 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 23 and for components in Table 24. Table 22 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 23 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Example for
DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 0 .. 9 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte look up table 1, 2, 4 look up table look up table
Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1)
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Table 24 1 2 3 4
DDR2 DRAM Nomenclature Values Coding HYB Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533 DDR2-400
Field Description INFINEON Component Prefix DRAM Technology
Interface Voltage [V] 18 T Component Density 256 [Mbit] 512 1G 2G
5 6 7 8 9
Raw Card Generation
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z S M R U
5+6 Number of I/Os
40 80 16
7 SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second 11 10 9 8
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F -3.7 -5
10 11
Speed Grade Die Revision
-3.7 -5 -A -B
Data Sheet
47
Rev. 0.91, 2004-06 09122003-FTXN-KM26
www.infineon.com
Published by Infineon Technologies AG

▲Up To Search▲

Price & Availability of HYS64T6402

	To Download HYS64T6402 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .